`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:17:29 03/28/2014 
// Design Name: 
// Module Name:    addrcalc 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////


module addrcal_bigboss(enable2,hcounter, vcounter,blank,addra, X1, Y1);
		
		input  enable2;
		input  blank;
		input [10:0] hcounter, vcounter;
		output reg [11:0] addra;
		input [10:0] X1,Y1;
		always @(hcounter,vcounter) begin
	
				if(enable2 && ~blank)begin

					if(hcounter>=X1 && hcounter<X1+49 && vcounter>=Y1 && vcounter<Y1+59) begin
						addra= (hcounter-X1)+(vcounter-Y1)*50;
					end
				end

				else begin
						addra=0;
					end
				end
	
	
	
		endmodule

